(ISSN: 2349-2082)

International Journal For Ignited Minds
 Published Article
Design of Low Power Double-Tail Dynamic Comparator Using Sleep Methods
SHRUTHI S , Prof. Ashwini N C
Analog to Digital Converter requires high speed, area efficient and low power comparators is forcing towards the use of Dynamic comparator. Higher power consumption will reduce the life time of the battery. The demand for long battery lifetime in applications poses the requirement for designing ultra-low power Dynamic comparators. In this paper an analysis on the power of single-tail and double-tail comparators are presented. Based on analysis a new Dynamic comparator is modified using Sleep methods for leakage power reduction even in small supply voltages like sleep, stack, sleepy-stack etc. Transient simulation results in a 250nm Tanner EDA tool confirm the analysis result. It is shown that among the proposed dynamic comparators, stack approach-Dynamic comparator reduces more power consumption.
Analog to digital conversion (ADC), CMOS, Dynamic comparator, Double Tail Comparator, Sleep Methods, Tanner EDA
 Download Article